A cost-effective clustered architecture
Ramón Canal, Joan-Manuel Parcerisa, Antonio M. González · 1999
In current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the floating-point cluster is extended to execute simple integer instructions. With minor hardware modifications to a conventional superscalar, the issue width can potentially be doubled without increasing the hardware complexity. In fact, the result is a clustered architecture with two heterogeneous clusters. In this paper we propose to extend this architecture with a dynamic steering logic that sends the instructions to either cluster. The performance of cluster architectures depends on the inter-cluster communication overhead and the workload balance. We present several schemes that use run-time information to optimise the trade-off between these figures. The evaluation shows that these schemes can achieve an average speed-up of 35% over a conventional 8-way issue (4 int + 4 fp) machine and that they outperform t...