Cell-aware analysis for small-delay effects and production test results from different fault models
Friedrich Hapke, Juergen Schloeffel, W. Redemund, Andreas Glowatz, Janusz Rajski, Michael M. Reese, Jeff Rearick, J. Rivers · 2011
This paper focuses on a new approach to significantly improve the overall defect coverage for CMOS-based designs with the final goal to eliminate any system-level test. This methodology describes the pattern generation flow for detecting cell-internal small-delay defects caused by cell-internal resistive bridges. Results have been evaluated on 1,900 library cells of a 32-nm technology. First production test results are presented from evaluating additional defect detections achieved with different fault models on a 45-nm design.