FPGA power efficient inverse lifting wavelet IP
Marco Grangetto, Maurizio Martina, Guido Masera, Gianluca Piccinini, F. Vacca, Maurizio Zamboni · 2001
In this paper a power efficient lifting-based wavelet transform IP, well suited for mobile and tetherless applications, is proposed. Recently, reconfigurable architectures, driven by new communication technology challenges and by mobile market explosion have moved developers' interest towards novel IP design strategies. Despite the increasing importance gathered by easily retargetable blocks, a lack of power conscious cores is felt by the developer's community. This IP is intended to be employed as the source coding kernel in many multimedia emerging algorithms. From post-place and route simulation a power dissipation of 36.6 mW has been obtained on a Xilinx XCV200E.