SCARM : A memory simulator with a compiler-assembler for the 32 bit ARM7 microprocessor
Nicole John A. Barahan, John Jerico M. Custodio, Joy Alinda R. Madamba, Christian Raymund K. Roque · 2011
This project is an implementation of a runtime memory simulator with a compiler-assembler for the ARM7 microprocessor with multi-core and floating point operation capability. Compiler support is extended to floating point computations. Also, the integrated development environment (IDE) features selective optimization for compilation. The target outputs are the assembly codes following the instruction set architecture (ISA) of the ARM7 and the equivalent binary instructions to generate the testbench for Synopsys VCS verification. The machine dependent optimizations of the compiler concentrate on register allocation and instruction scheduling techniques to further take advantage of the ARM7 architecture.