Adding a vector unit to a superscalar processor
Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero · 1999
The focus of this paper is on adding a vector unit to a superscalar core, as a way to scale current state of the art superscalar processors.The proposed architecture has a vector register file that shares functional units both with the integer datapath and with the floatingpoint datapath.A key point in our proposal is the design of a high performance cache interface that delivers high bandwidth to the vector unit at a low cost and low latency.We propose a double-banked cache with alignment circuitry to serve vector accesses and we study two cache hierarchies:one feeds the uector unit from the Ll; the other from the L.2.Our results show that large IPC values (higher than IO in some cases) can be achieved.Moreover the scalability of our architecture simply requires addition of functional units, without requiring more issue bandwidth.As a consequence, the proposed vector unit achieves high performance for numerical and multimedia codes with minimal impact on the cycle time of the processor or on the performance of integer codes.Peqlission lo make 'iigital or hard copies o('all or part of this work fbl pcrsonal or classroom use is granted without fee provided that @es are ,lOt lnade or distributed for profit or cotnmercial advantage and that copjes bcdr tjlis tl&ce ad the full ci talion on the lht paye.To CWY otherwise, Lo republish, to post on servers or to rsdistrihute to listsrequitscs prior qvdic permksion andior a fee.ICS '99 Rhodes '3cecc