Bit‐serial vlsi implementation for an optimized transmultiplexer design
Francky Catthoor, Hugo De Man, Joos P. L. Vandewalle · International Journal of Circuit Theory and Applications · 1987
Abstract The silicon implementation of a transmultiplexer system, from the high level description up to the floor‐plan, is presented. the described realization allows to integrate an entire 12‐channel TDM‐FDM transmultiplexer system on a silicon area of less than 80 mm2in a 5 μm single‐metal race‐free dynamic CMOS technology, making use of an available bit‐serial standard‐cell library. At the architectural level, a hardware‐sharing transformation combined with a number of optimizations for the coefficient quantization and the choice of the data word‐length, have allowed for a global area‐reduction of almost 50 per cent. First a mainly manual approach has been investigated, where the hierarchical decomposition has been exploited to perform global and local optimizations in terms of the hardware. Later on, based on this experience, it has been employed as a major test vehicle for the CAD tool‐box of the bit‐serial silicon compiler1,2which has been developed during the pilot phase of an ESPRIT research project at our laboratory. Extensive use has been made of programs for filter synthesis, optimization, bit‐serial mapping, delay management and standard‐cell placement and routing. the results obtained with both design strategies are compared. This research has given a concrete example of how systems, filter, network, circuit and CAD experience can be effectively combined into a VLSI design.