A Cell Selection Policy For An Input-Buffered Packet Switch
Azeddine Bilami, Mustapha Lalam, Mehammed Daoui, B. Djamah · International Journal of Computers and Applications · 2006
The literature contains many theoretical solutions to the design of high-performance packet switches, related to buffering, selection, and routing functionalities. Different selection policies and scheduling algorithms providing 100% throughput, such as MSM, MWM, and the like, have been proposed. However, in practice many of them introduce a high complexity and are not feasible. In this paper, we suggest a simple cell selection policy implemented by hardware for an input-queuing architecture using a multistage interconnection network. The proposal is described and simulated using a VHDL language. Performances in terms of delay, throughput, and cell loss are evaluated.