Design methodology of a 200MHz superscalar microprocessor
Toshihiro Hattori, Yusuke Nitta, M. Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, R. Satomura · 1998
A new design methodology focusing on high speed operation and short design time is described for the SH-4 200MHz superscalar microprocessor. Random test generation, logic emulation, and formal verification are applied to logic verification for shortening design time. Delay budgeting, forward/back annotation, and clock design are key features for timing driven design.