Low overhead design for programmable logic array with testability
K. C. WEI, Jinn-Jong Sheu, B. D. LIU · International Journal of Electronics · 1994
A new design to reduce the overhead required for a fully testable PLA is proposed. This design rearranges and groups the product lines into partitions. Then, one extra output line per partition is added to make the whole PLA testable. The silicon area overhead required by this design is significantly less than those of previous methods.