A parity bit signature for exhaustive testing
Sheldon B. Akers · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1988
A parity bit signature particularly well suited for exhaustive testing techniques is defined and discussed. The discussion is concerned not only with the proposed parity bit signature itself, but also with the general problem of evaluating its effectiveness relative to a given implementation. In addition to such desirable properties as uniformity and ease of implementation, it is shown to be especially amenable to efficient fault coverage calculations.>