A memoryless Viterbi decoder for LTE systems
Chu Yu, Yu-Shan Su, Bor-Shing Lin, Po‐Hsun Cheng, Sao‐Jie Chen · 2012
This paper presents a novel memoryless Viterbi decoder (VD) with a 4-level soft decision for long term evolution (LTE) systems. Based on the proposed architecture, the survivor memory can be eliminated totally, which will significantly reduce 50% of the total power dissipation. Finally, the proposed design consumes approximately 23.4K gates using 0.18 μm CMOS technology, and its power consumption is approximately 7.5 mW at 80 MHz.