TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections
Kevin Chung, Jonathan Rose · 1992
This paper describes TEMPT, a technology mapping algorithm aimed at exploring FPGA architectures with hardwired connections. Such FPGA architectures may be important because hard-wired connections are much faster and smaller than the programmable connections between basic logic blocks that they replace. TEMPT maps a network of basic blocks to a netlist of hard-wired logic blocks (HLBs), in which each HLB consists of several basic blocks hard-wire connected in an arbitrary tree topology, and optimizes either speed or area. TEMPT is as effective as the Xilinx 4000 CLB mapper, PPR, when minimizing CLBs to implement a set of MCNC benchmarks. Using TEMPT we demonstrate empirically how many HLBs are significantly faster than FPGAs without hard-wired links. Also, we demonstrate several HLBs that exhibit superior logic density to the Xilinx 4000 CLB.