Transactions make a comeback for big system design
C. Edwards · Electronic Systems and Software · 2003
The pain of trying to get software ready to hit the same deadline as hardware is forcing chip designers to build higher level models. For transaction-level modelling - a technique that promises to slash design time for software-intensive systems - it has taken more than 10 years for the technique to begin to move out from a few advanced users. A couple of years ago ICL killed off the VHDL+ tool although members of the team have gone on to form a startup called Spiratech to promote the underlying methods. But, at the Design, Automation and Test in Europe (DATE) conference in Munich in March 2003, transaction level modelling made a comeback as designers from ARM Holdings, Infineon Technologies and STMicroelectronics said they had been using the technique successfully on their own projects.