The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor
D. Wendel, Reddieswara Naidu Kalla, R. Cargoni, J. Clables, Joshua Friedrich, Roland Frech, J. Kahle, Balaram Sinharoy, William J. Starke, S. Taylor, S. Weitzel, Sang-Hoog Chu, S. Islam, Victor V. Zyuban · 2010
POWER7TMthe next generation processor of the POWERTMfamily is introduced. The 8-core chip, supporting 32 threads, is implemented in 45 nm 11 M CMOS SOI. The 32 kB L1 caches feature 1 read port banked write for the l-cache and 2 read ports banked write for the Dcache. The on-chip cache hierarchy consists of a 256 kB fast, private SRAM L2 and a 32MB shared L3, implemented in embedded DRAM.