A still-image encoder based on adaptive resolution vector quantization featuring needless calculation elimination architecture
M. Fujibayashi, Tomohiro Nozawa, Takahiro Nakayama, 康平 望月, M. Konda, Koji Kotani, S. Sugawa, T. Ohmi · IEEE Journal of Solid-State Circuits · 2003
A still-image encoder based on vector quantization (VQ) has been developed using 0.35-μm triple-metal CMOS technology for encoding a high-resolution still image. The chip employs the needless calculation elimination method and the adaptive resolution VQ (AR-VQ) technique. The needless calculation elimination method can reduce computational cost of VQ encoding to 40% or less of the full-search VQ encoding, while maintaining the accuracy of full-search VQ. AR-VQ realizes a compression ratio of over 1/200 while maintaining image quality. The processor can compress a still image of 1600×2400 pixels within 1 s and operates at 66 MHz with power dissipation of 660 mW under 2.5-V power supply, which is 1000 times larger performance per unit power dissipation than the software implementation on current PCs.