High-bandwidth and low latency from a three-dimensional reconfigurable interconnect
John William Morris Jr., Sonny Tham · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1999
A high bandwidth, low latency processor interconnect has been constructed using off-the-shelf FPGAs and a small amount of additional logic. The Achilles system comprises a router in which the main circuit elements (the FPGAs) have been placed on ten small PCBs and connected together to make a router `stack' and a PCI interface. On the first prototype, channel bandwidth has been measured at 28 Mbytes/second and latency was measured to be 800 ns. The newer low-voltage FPGAs will be used in the next Achilles variant, allowing the bandwidth capability will increase to close to the theoretical maximum for PCI bus. The router stack and PCI interface also has application as a general purpose reconfigurable processor which may be arbitrarily extended by adding further stacks to the system.