A high speed image codec VLSI for document retrieval
F. Sato, M. Murayama, Shuichi Sumita, K. Adachi · IEEE Transactions on Circuits and Systems · 1989
A new high-speed expansion scheme for binary image data compressed using the MMR code is presented. The proposed scheme enables the output image data to flow at nearly the maximum data flow rate of 1 byte per machine cycle, even for a rather complicated image, such as CCITT reference document No. 4. A key to this performance is the proposed concept of parallel image streaming combined with bit-parallel, concurrent decoding of the next codeword. Based on these concepts, a VLSI chip was designed, fabricated, and evaluated. The effectiveness of the scheme is evidenced by the fact that any of the CCITT reference documents are expanded in 0.11 to 0.13 s.>