CMOS analog circuit stack generation with matching constraints
R. Naiknaware, Terri S. Fiez · 1998
Abstiact-An efficientCA1OStramistor stack generation procedure for analog circuits is d=eribed.The matchmg mqutiments are used as the primary comtraint on the artatog layou~however,parasitic mpacitances and area eomideratiorrsare also included.A designer chosenarbitrary circuit partition from the srhematic a be used to generate the corresponding layout as an optimum stack of transistors with completeintra-module connectivity.The port structures are consideredm part of the modulearea and parasitic optbrdntion procedure.The results are demonstrated through an exampleand a completeebip layout of a high-resolutiondelta-sigmaartafo~ to-digitalconverter.