Effects of scaling a coarse-grain reconfigurable array on power and energy consumption
Waqar Hussain, Tapani Ahonen, Jari Nurmi · 2012
In recent past, we scaled a 4 × 8 processing element (PE) template-based Coarse-Grain Reconfigurable Array (CGRA) to a 4×4, 4×16 and 4×32 PE CGRA and generated matrix-vector multiplication (MVM) accelerators from each one of them. Furthermore, on each of the accelerators, MVM kernels of order N = 4; 8; 16; 32 were mapped. In this paper, we have estimated the power and energy consumption by generating the postfit gate-level netlist of each accelerator for a Field Programmable Gate Array as target platform. Based on our measurements, we have studied the effects of scalability of a CGRA on power and energy consumption.