The road ahead in CPLD & FPGA design methodology (panel)
Rhondalee Rohleder, John Birkner, D. Faria, Steve Golson, R K Beachler, B. Kleinman, Mike Dini, Bob Donaldson, Davie Kohlmeier · 1997
Large capacity CPLD and FPGA design opportunities and challenges are explored by this panel. As densities grow beyond 20,000 gates, there is a disconnect between the cutting-edge EDA tools featured in trade shows and the more ordinary toolsused by the typical programmable logic designer as s/he moves to a higher level design methodology. A three-to-five year roadmap will guide this discussion of the future of synthesis and simulation, the impact of HDLs on complex devices, and the role of intellectual property and universal tools in the CPLD & FPGA designscape.