Reducing memory bottlenecks in embedded, parallel image processors
S. McBader, Peter David Lee · Electronics Letters · 2003
Owing to the sequential nature of memory interfaces, as well as the growing processor-memory performance gap, the design of parallel image processors is often faced with a challenge in deciding memory organisation and distribution. This work addresses the problem of memory access bottlenecks in parallel digital image processors and presents one solution which demonstrates up to 93.4% reduction over standard sequential methods.