Integration of dual channel timing formatter system for high speed memory test equipment
Jaeseok Park, Ingeol Lee, Young-Seok Park, Sung-Geun Kim, Kyung Ho Ryu, Dong‐Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong‐Ook Jung, Woo‐Young Choi, Sungho Kang · 2012
This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.