VLSI implementation of a signal interpolator chip for high‐speed all‐digital data modems
Marco Luise, Roberto Roncella · European Transactions on Telecommunications · 1994
Abstract This paper describes the structure of a signal interpolator chip to be used in medium‐to‐high data rate digital modems, based on the so‐called “Systolic Macrocells” design style. In particular, we focus on a third‐order polynomial interpolation algorithm, as a good trade‐off between the contrasting needs of high accuracy and low complexity/cost. We also present a concise description of the architecture of the chip through a functional description of the main basic systolic macrocells it is composed of. Despite the apparent complexity of the architecture, the basic cells of each bit‐level systolic array are remarkably simple and homogeneous: they are mainly composed by delays and summing elements such as full and half adders, so that their realization does not represent a difficult design task. The interpolator chip has been completely laid out assuming a 1.2 μ m CMOS technology and occupies a silicon area of 5 × 4.5 mm2, pad included. In particular, we envisage an operating clock frequency of 70 MHz, so that the chip can process sequences of 8 bit words at the rate of 17.5 MSamples/s with a power supply requirement of less than 0.5 W.