A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach
T. Fujii, Hideya Horikawa, Tohru Kikuno, N. Yoshida · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1987
In this paper, we present a new approach for the one-dimensional gate assignment problem. The original minimization problem is transformed into a restricted problem, and then a new heuristic algorithm is applied to it. The solution obtained by the algorithm is interpreted as a solution for the original problem. The whole process of the approach has been implemented and tested with various examples. Experimental results show that our approach can approximately produce optimum solutions.