Random clocking induced DPA attack immunity in FPGAs
Yousaf Zafar, Jihan Park, Dongsoo Har · 2010
For FPGA-centric implementations a countermeasure enhancing immunity against differential power analysis (DPA) attacks is proposed, that introduces pseudorandom clocking scheme to Advanced Encryption Standard (AES) cipher based multi-clock system with embedded single inverter ring oscillators (SIROs).