Multiple sub-row buffers in DRAM
Nagendra Gulur, Raman Manikantan, Mahesh M. Mehendale, R. Govindarajan · 2012
The twin demands of energy-efficiency and higher performance on DRAM are highly emphasized in multicore architectures. A variety of schemes have been proposed to address either the latency or the energy consumption of DRAMs. These schemes typically require non-trivial hardware changes and end up improving latency at the cost of energy or vice-versa.