A hybrid architecture for neurocomputing (abstract)
W.E. Mattis · 1990
A hybrid (analog/digital) architecture is described for realization as a neurocomputing element. The architecture is derived by examination of the operation of a typical neural network. Specifically, the outputs of neurons are connected to other neurons through axons and dendrites, weighted at the synaptic junction. The next state of any neuron is determined by the sum of the weighted inputs from all other neurons. Neural membranes, modeled as sigmoidal functions, determine the neuron response (output waveform). From this biological description, the architecture can be realized. The synapses, or weight vectors, for the neural network, are stored in N registers in digital from. It is assumed that these weights are known previously, or are calculated (updated) after each complete cycle from a learning law. The previous state of each neuron is stored in analog form in a register. Interconnecting the memory (synapses) with the stored neuron states are switches, multipliers (for multiplying a digital weight with a neuron state), summers (to accumulate the individual weight-neuron state products), and sigmoidal functions, to determine the next neuron output. Over a cycle, the sequence is such that each prior neuron state is multiplied by the appropriate weight and these products summed. Near the end of the cycle, this value is passed to the sigmoidal function, and the new neuron state found and stored for the next cycle. For complete implementation, hardware is specified, including the use of a charge-coupled device (CCD) register for the neuron state, digital RAM (random access memory) for the weight storage, and the use of multiplexers and multiplying digital to analog (D/A) converters to compute the individual weight-neuron state products for summation.