High-throughput low-cost VLSI architecture for AVC/H.264 CAVLC decoding
G.G. Lee, Chun‐Chih Lo, Y.-C. Chen, Hung‐Yin Lin, M.-J. Wang · IET Image Processing · 2010
This study develops a low-cost very-large-scale-integration (VLSI) hardware architecture for entropy coding with increased throughput using the statistical properties of context-based adaptive variable-length coding (CAVLC) in AVC/H.264. Statistical analyses show that better symbol length prediction was achieved by breaking the recursive dependency among codewords for the multi-symbol decoder implementation. The proposed CAVLC decoder easily meets the real-time requirements for high definition (HD) (1920×1088) applications. The clock speed is only 13 MHz under the best case scenario.