The design of HIMAC coprocessor based on HINOC 2.0
Deng Chen, Weitao Pan, Jinyuan Zhang, Chun Liu, Zhiliang Qiu, Zhang Shi, Bing Zhang, Chun Yang, Cheng Zhang · 2014
In this paper, we introduced a hardware acceleration coprocessor design of HIMAC 2.0 in HINOC 2.0 system. The main function of HIMAC 2.0 have been detailed and compared with corresponding part of HINOC 1.0. By building the self-testing platform and designing the test scheme, the design, which has been simulated and has passed the FPGA verification, realizes 1Gbps data transmission between HIMAC 2.0 and Ethernet.