Modeling ASIC memories in VHDL
E Balaji, Praveen Thaggikuppe Krishnamurthy · European Design Automation Conference · 1996
Memories are all important component in ASIC designs. With increasing design complexities, there is need to model memory devices with a high level of accuracy and simulation efficiency. This paper describes the functional/timing aspects of VHDL memory models, their implementation, and various issues involved. The paper also presents a generic interface package used in the development of memory models.