Magnetic-bubble VLSI logic system
Jyh-Ping Hwang, J. C. Wu, F. B. Humphrey · IEEE Transactions on Magnetics · 1984
A magnetic bubble systolic array string-pattern matcher is presented demonstrating that bubble VLSI logic systems are appropriate for back-end processing. The VLSI systolic algorithm matches the intrinsic features of logic devices using bubbles. The essential components (AND/OR, comparator, and switch) of the bubble string-pattern matcher have been successfully implemented in current-access perforated-sheet devices, giving an 12% overlapped bias margin at 2 mA/μm drive current and 1 MHz operating frequency. The performance evaluation at the system level reveals that a bubble string-pattern matcher offers speed improvement of 4 times over conventional Winchester disk - semiconductor processor system. The performance improvement will increase with the increasing bubble memory density and data base size.