Analysis of Reed Solomon error correcting codeson reconfigurable hardware
Anne Franssens · 2008
This thesis describes the advantages and disadvantages of using architectures consisting of multiple different (types of) processors. Such architectures are better known as heterogeneous architectures. The research is focussed on de- termining processing power and energy efficiency, based upon the mapping of a Reed Solomon (RS) error correcting decoder on a reconfigurable architecture. Parts of the RS decoder that are not implemented, will be executed on a General Purpose Processor which can communicate with the reconfigurable hardware, which is better known as a heterogeneous architecture. The GPP used, is an ARM, and the reconfigurable architecture used is a Montium. The RS algorithms are implemented to derive conclusions as to which architecture is favorable for implementation of the different RS sub-blocks, and how processing power and energy e�ciency relate to other architectures.