Optimised multiply/accumulate architecture for veryhighthroughput rate digital filters
B.P. McGovern, Roger Woods, Catherine McAllister · Electronics Letters · 1995
A new modified circuit for implementing high performance IIR filters based on a pipelined multiply-accumulate (MAC) processor is proposed. Clever deployment of latches in the circuit allows the results to be generated once every cycle thereby providing increased performance with reduced size and power consumption over previously designed circuits.