An FPGA Based Performance Analysis of Pipelining and Unrolling of AES Algorithm
C. Nalini, Nagaraj, P.V. Anandmohan, D.V. Poornaiah, Veena Kulkarni · 2006
This paper proposes an efficient solution to combine Rijndael encryption and decryption in one FPGA design, with a strong focus on low area constraints and high throughput. This Rijndael implementation runs its symmetric cipher algorithm using a key size of 128 bits, mode called AES128. In this paper a fully pipelined AES encryptor/decryptor core is presented. Various approaches for efficient hardware implementation of the Advanced Encryption Standard algorithm based on architectural optimization and algorithmic optimization are discussed, implemented. and their performance results obtained are compared with previous reported designs. The proposed design uses the widely used lookup- table implementation of S-box n terms of ROM and Block RAM and is easily pipelined to achieve high throughput rate and the advantage of sub-pipelining can be further explored. The pipelined architecture can be made to toggle between the encryption and decryption modes without the presence of any dead cycle. Using the proposed architecture, a fully sub-pipelined AES core with both inner and outer round pipelining and a 2 sub-stages in each round unit realized using Virtex-E devices can achieve a throughput of 30.88Gbps at 241.313 MHz and 4626 CLB Slices with 160 BRAM'S. in non-feedback modes, which is faster and more efficient than the fastest previous FPGA implementation known to date.