High-speed architectures for GHASH based on efficient bit-parallel multipliers
Jimei Wang, Guochu Shou, Yihong Hu, Zhigang Guo · 2010
GHASH is the authentication part of Galois Counter Mode (GCM) which can provide encryption and authentication simultaneously, its core is based on the GF(2128) multiplier. A four-parallel architecture for GHASH which is applied to authentication for high-speed access networks is proposed, and its core GF(2128) multiplier is implemented by two kinds of general bit-parallel structures. We implement the four-parallel GHASH on FPGA platform, the synthesis results show that the throughput can reach 123.053 Gbps and 120.086Gbps when use the improved M multiplier and the Karatsuba-Ofman multiplier as its core respectively. So they both meet the demands of high-speed access network's applications.