A FPGA-based hardware implementation of generalized profile search using online arithmetic
Emeka Mosanya, Eduardo García Sánchez · 1999
Article Free Access Share on A FPGA-based hardware implementation of generalized profile search using online arithmetic Authors: Emeka Mosanya Logic Systems Laboratory, Swiss Federal Institute of Technology, INN Ecublens. CH-1015 Lausanne, Switzerland Logic Systems Laboratory, Swiss Federal Institute of Technology, INN Ecublens. CH-1015 Lausanne, SwitzerlandView Profile , Eduardo Sanchez Logic Systems Laboratory, Swiss Federal Institute of Technology, INN Ecublens. CH-1015 Lausanne, Switzerland Logic Systems Laboratory, Swiss Federal Institute of Technology, INN Ecublens. CH-1015 Lausanne, SwitzerlandView Profile Authors Info & Claims FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arraysFebruary 1999 Pages 101–111https://doi.org/10.1145/296399.296436Published:01 February 1999Publication History 2citation434DownloadsMetricsTotal Citations2Total Downloads434Last 12 Months6Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF