An SoC With 1.3 Gtexels/s 3-D Graphics Full Pipeline for Consumer Applications
Donghyun Kim, Fu-Lai Chung, Chang-Hyo Yu, Chungman Kim, I. Lee, Jaewan Bae, Young‐Jin Kim, Jeong‐Hoon Park, Seung Hwan Kim, Yong‐Hwa Park, NakHee Seong, J.-A. Lee, Jaewon Park, Sehyeong Oh, Seh-Woong Jeong, L.-S. Kim · IEEE Journal of Solid-State Circuits · 2005
A high-speed three-dimensional (3-D) graphics SoC for consumer applications is presented. A 166-MHz 3-D graphics full pipeline engine with performance of 33 Mvertices/s and 1.3Gtexels/s, and 333-MHz ARM11 RISC processor, and video composition IPs are integrated together on a single chip. The geometry part of 3-D graphics IP provides full programmability in vertex and triangle level, and two-level multi-texturing with trilinear MIPMAP filtering are realized in the rasterization part. Per-pixel effects such as fog effects, alpha blending, and stencil test are also implemented in the proposed 3-D graphics IP. The rasterization architecture is designed for reducing external memory accesses to achieve the peak performance. The chip is fabricated using 0.13/spl mu/m CMOS technology and its area is 7.1/spl times/7.0mm/sup 2/.