Verification of a Timed Multitask System With Uppaal
Houda Bel Mokadem, Béatrice Bérard, Vincent Gourcuff, Olivier De Smet, Jean‐Marc Roussel · IEEE Transactions on Automation Science and Engineering · 2010
System and program verification has been a large area of research since the introduction of computers in industrial systems. It is an especially important issue for critical systems, where errors can cause human and financial damages. Programmable Logic Controllers (PLCs) are now widely used in many industrial systems and verification of the corresponding programs has already been studied in various contexts for a few years, for the benefit of users and system designers. First restricted to an untimed setting, verification was recently extended to systems where quantitative constraints are needed, possibly related to time elapsing. For instance, timed features like TON (Timers ON delay), used in PLC programs, were modeled with timed automata, thus increasing the size of the verification problems addressed.