Designing optimized forward residue number systems IP blocks converters from a network interface
Giannis Petrousov, Minas Dasygenis · 2014
Contemporary digital circuits demand a fast time to market period, and consequently a rapid prototype design exploration. Fast design space exploration requires tools that given a set of input constrains, generate the HDL definitions that implement the given functionality. Furthermore, residue number system (RNS), a non-conventional arithmetic system, has been proposed as a viable alternative for hardware acceleration, due to it's carry free nature. In this context, we present the first web accessible EDA tool that can generate custom synthesizable forward residue number binary-to-RNS converters, for a specific input bit width and a moduli base. To the best of our knowledge, our novel tool is the first one to automate the design of forward residue number system converters and simultaneously provide custom test benches to verify their correctness. Our synthesized circuits on Xilinx Virtex 6 FPGA, operate up to 783 Mhz.