Adapting cache line size to application behavior
Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gupta, Alexandru Eugen Nicolau, Xiaomei Ji · 1999
A cache line size has a significant effect on miss rate and memory traffic. Today's computers use a fixed line size, typically 32B, which may not be optimal for a given application. Optimal size may also change during application execution. This paper describes a cache in which the line (fetch) size is continuously adjusted by hardware based on observed application accesses to the line. The approach can improve the miss rate, even over the optimal for the fixed line size, as well as significantly reduce the memory traffic.