Low power design method in high level synthesis with multiple voltages
Wei Chen, Guangshun Li, Xiujuan Zhang · 2010
A new method that integrated high level synthesis and floorplan are proposed to reduce the total power dissipation. Function units are sorted into several clusters according to their working voltages. Floorplan are executed with the information of cluster gained from high level synthesis, and then the high level synthesis resolutions are adjusted iteratively with the interconnect information and switching activity gained from floorplan. Not only function unit power and interconnect power, but also the voltage converting power can be reduced in our method. Experimental results indicate that, under the given resource and latency constrains, the interconnect power, level convert power and total power of our method can be reduced by 30.4%, 35.1% and 22.9% respectively.