High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4
Per Karlström, Andreas Ehliar, Dengcheng Liu · IET Computers & Digital Techniques · 2008
There is increasing interest about floating-point arithmetics in field programmable gate arrays (FPGAs) because of the increase in their size and performance. FPGAs are generally good at bit manipulations and fixed-point arithmetics, but they have a harder time coping with floating-point arithmetics. An architecture used to construct high-performance floating-point components in a Virtex-4 FPGA is described in detail. Floating-point adder/subtracter and multiplier units have been constructed. The adder/subtracter can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade −12).