A novel multi-core processor for communication applications
Ruijin Xiao, Heng Quan, Kaidi You, Bei Huang, Xiaoyang Zeng, Zhiyi Yu · 2010
This paper proposes a novel multi-core processor with SIMD(Single Instruction Multiple Data) ISA (Instruction Set Architecture) and extended register file for communication applications. To acquire better parallel computing capability, we implement SIMD ISA and increase the number of register file from 32 to 64. 5×5 homogeneous 2-D mesh NoC (Network-on-Chip) topology is adopted to further enhance the parallelism, scalability and programmability. RS (Reed-Solomon) (255,239,8) decoding algorithm is implemented to evaluate the performance. Simulation result shows it could achieve 2.175 Gbps of throughput in worst case of RS 8-error incoming codeword under a maximum 350MHz clock frequency at SMIC 0.13um worst process corner, and the throughput is higher than other published implementations.