Automatic test generation for verifying microprocessors
Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero · IEEE Potentials · 2005
A pipelined processor with a high-level behavioral HDL description is presented in this paper. It generates a set of effective test programs by using a simulator, which is able to evaluate with respect to an RTL coverage metric. The proposed optimizer is based on a technique called microGP, an evolutionary system able to automatically device and optimizes the program written in an assembly language. Quantitative coverage measurement presented will guide the test-program generation. The approach is fully automatic and broadly applicable. The minimal test set with the programmable coverage is attained.