Demonstration of 32nm half-pitch electrical testable NAND FLASH patterns using self-aligned double patterning
Shiyu Sun, Chris Bencher, Yong Mei Chen, Huixiong Dai, Man-Ping Cai, Jaklyn Jin, Pokhui Blanco, Liyan Miao, Ping Xu, Xumou Xu, James Yu, Raymond Hung, Shiany Oemardani, Osbert Chan, Chorng‐Ping Chang, Chris S. Ngai · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2009
Self-Aligned Double patterning (SADP) technology has been identified as the main stream patterning technique for NAND FLASH manufacturers for 3xnm and beyond. This paper demonstrates the successful fabrication of 32nm halfpitch electrical testable NAND FLASH wordline structures using a 3-mask flow. This 3-mask flow includes one critical lithography step and two non-critical lithography steps. It uses a positive tone (spacer as mask) approach to create 32nm doped poly wordlines. Electrical measurements of line resistance are performed on these doped poly wordlines to demonstrate the capability of this patterning technique. Detailed results and critical process considerations, including lithography, deposition and etch, will be discussed in this paper.