A prolog machine based on vlsi algorithms
Yasuro Shobatake, Hideo Aiso · Systems and Computers in Japan · 1989
Abstract This paper proposes a Prolog direct executer called PMV‐2. To alleviate the von Neumann bottleneck, PMV‐2 is provided with a number of processing elements, each of which stores a term symbol. Using the processing elements, the operations for terms can be executed in parallel. To simplify the algorithm for mapping the tree‐structured data onto processing elements, data are represented by a format called symbol‐line expression. Tree‐structured data with this expression are mapped onto an array which has straight‐line arrangement for processing elements. The configuration of the tree‐structured data on the processing element array can be modified using the methods called Partial Global Communication and Partial Shift. To implement a large number of processing elements, PMV‐2 is constructed based on the VLSI algorithms. A performance evaluation has been made, revealing that the processing speed of approximately 450 kLips is obtained by PMV‐2, which is nearly the same as that of a presently available high‐speed Prolog system with a compiler.