POWER2 instruction cache unit
Jama Barreh, Robert Golla, L. B. Arimilli, P. J. Jordan · IBM Journal of Research and Development · 1994
This paper describes the instruction cache unit (ICU) of the IBM POWER2™ processor, with emphasis on improvements over the original POWER ICU design. The POWER2 ICU incorporates a new compare-branch scheme that minimizes processing time penalties, a second branch processor, increased branch look-ahead capability, and doubled instruction-fetch and instruction- dispatch bandwidth.