Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs
Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera · 2008
FPGAs in future deep submicron fabrication process will suffer from drastic speed and yield loss caused by device variations. We propose variation-aware reconfiguration which utilizes variations for performance enhancement. To utilize random variations for performance enhancement, optimizing each device from a common initial configuration is better than producing optimized configurations according to detailed measurement results because it is very hard to measure detailed variation maps chip by chip when random uncorrelated variations are dominant. In the critical path reconfiguration scheme, an initial configuration is gradually optimized chip by chip according to the delay variations. We apply the track swapping procedure to critical path reconfiguration which obtains an optimized configuration to repeat measurement and reconfiguration. First we configure all fabricated FPGAs with a common configuration data without considering variations. The configuration of each die is optimized to reroute the critical paths by choosing a faster path. To reroute a critical path we swap a wire track on a critical path with the adjacent track. It can be realized to use switch blocks with more flexibility. We implement the track swapping to VPR and experiment performance enhancement by applying the track swapping to LGSynth93 benchmark circuits. The average speed and yield enhancements are 2.57%, 26.01% respectively when the standard deviation of random variations is 10.0%