Decoder-based interconnect structure for multi-context FPGAs
Andrea Lodi, Luca Ciccarelli, A. Cappelli, Fabio Campi, M. Toma · Electronics Letters · 2003
Multi-context FPGAs could be a convenient approach for run-time reconfiguration, but they suffer from large area occupation. To overcome this limitation a new decoder-based interconnection architecture has been studied. Both a multi-context memory cell and a decoder scheme are presented to achieve minimum area occupation.