Error-Correcting Code Aware Memory Subsystem
Wooyoung Jang · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2014
An error-correcting code (ECC) immune to bit errors has been widely used in reliable computer systems. However, ECC techniques can make memory performance severely degraded since incomplete-word write requests lead to inefficient read-to-write (RTW) and write-to-read operations of synchronous dynamic random access memory. In this paper, we propose a memory subsystem efficient for ECC operations. Our key idea is that the RTW operations causing incomplete-word write requests are split and grouped into independent read and write operations, and then the grouped read and write operations are individually scheduled for the optimal memory performance under application constraints. Experimental results show that the proposed ECC-aware memory subsystem achieves 17% shorter memory latency, and 12% higher memory utilization, on average, than the latest conventional memory subsystems on industrial multimedia applications. Moreover, the ECC-aware memory subsystem improves up to 2.5 times higher memory performance on synthetic benchmarks.